1. Field of the Invention
The present invention relates to an analog to digital converter for converting an analog signal, especially, an analog signal having periodically appearing constant dc levels as a television picture signal, to a digital signal with high exactness, and without being affected by dc drift occuring in the signals and circuit elements.
2. Description of the Prior Art
In converting a television picture signal in the form of an analog signal to a digital signal, for instance, to a PCM signal, and then converting again the digital signal received on the receiving side to an analog signal, so as to reproduce television pictures with high quality, it is required that the analog to digital converting speed should be set at 86 Mbits/sec (10.74 MHz, 8 bits/word), for example, as for the present NTSC standard system. This is because one clock interval is about 93 nano seconds, and it is required that there should be 8 bits for each picture element. Besides, so as to prepare the time for holding a sampled signal within such a short interval, it is required that the operating duration of the respective circuit elements be less than 2-3 nano seconds.
Digital circuit elements having such a high operating speed are obtained with the use of high speed logic circuit elements, for instance, ECL (emitter coupled logic type) and others. At present, however, such analog circuits as voltage comparators and others can hardly act with such a high speed when they employ transistors having cut-off frequencies of 5 GHz as discrete elements. Accordingly, the entire equipment becomes unavoidably expensive.
In a feed-back type analog to digital converter, for instance, that shown in "On the Experimental Ultra-High Speed CODEC" ("OKIDEN Review," vol. 37, No. 4, Dec. 1970, pp 48-64), which is produced with the use of discrete circuit elements for converting a television picture signal to a digital signal, such a high speed conversion as mentioned above has been realized. But, it is impossible at present to realize such a high speed conversion with the use of integrated circuit elements in the feed-back type analog to digital converter.
In a cascade type analog to digital converter, which is used in place of the feed-back type, low speed circuit elements can be used for respective converting stages, because the input signal to be converted to a digital signal is serially delayed by delay circuits of the respective converting stages. That is, the cascade type analog to digital converter consists, as shown in FIG. 1, of a specified number of unit converting stages connected in cascade. Each of the unit stages consists of a delay circuit 4 used for adjusting the signal timing by delaying the input analog signal, for example, a television picture signal. The input analog signal is applied to an input terminal 1 so as to be converted to a digital signal, a comparing circuit 2 which compares the input signal with a reference signal and forms a digital signal of "1" or "0" as an output resulting from the comparison, a digital to analog converter 3 which converts the digital signal derived from the comparator 2 to a corresponding analog signal, and an operational amplifier 5 which forms a differential output signal of the input signal derived from the delay circuit 4 and the analog signal derived from the converter 3, as an input signal of the next stage. The digital signal derived from the comparator 2 is also taken from a terminal 6 as an output of this stage through a delay circuit 7.
Although slow speed circuit elements can be used for the cascade type analog to digital converter, it requires delay circuits, operational amplifiers and other circuits having respectively small dc drifts. The dc components of the signals to be treated are varied under the influence of dc drifts in these circuit elements, and consequently the exactness of the action is lowered.